/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  hipciec_ap_iob_rx_com_reg_reg_offset.h
 * Department    :  CAD Development Department
 * Author        :  xxx
 * Version       :  1.0
 * Description   :  PCIE Controller 5.0  Version 200
 * Others        :  Generated automatically by nManager V5.1
 * History       :  xxx 2021/10/25 15:27:37 Create file
 */

#ifndef __HIPCIEC50_AP_IOB_RX_REG_REG_OFFSET_H__
#define __HIPCIEC50_AP_IOB_RX_REG_REG_OFFSET_H__

/* HIPCIEC50_AP_IOB_RX_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE                       (0x4000)

/******************************************************************************/
/*                      HiPCIECTRL50V200 HIPCIEC50_AP_IOB_RX_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_0_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x0)    /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_1_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_2_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_3_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x60)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_4_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x80)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_5_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA0)   /* IOB RX address transition unit control register0.Common information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_0_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4)    /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_1_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_2_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x44)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_3_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x64)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_4_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x84)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_5_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4)   /* IOB RX address transition unit control information register1.TLP information. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_0_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8)    /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_1_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_2_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x48)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_3_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x68)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_4_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x88)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_5_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8)   /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC)    /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x6C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8C)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC)   /* IOB RX address transition unit region size low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10)   /* IOB RX address transition unit base address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30)   /* IOB RX address transition unit base address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x50)   /* IOB RX address transition unit base address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x70)   /* IOB RX address transition unit base address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x90)   /* IOB RX address transition unit base address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB0)   /* IOB RX address transition unit base address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x54)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x74)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x94)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB4)   /* IOB RX address transition unit base address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18)   /* IOB RX address transition unit target address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38)   /* IOB RX address transition unit target address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x58)   /* IOB RX address transition unit target address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x78)   /* IOB RX address transition unit target address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x98)   /* IOB RX address transition unit target address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB8)   /* IOB RX address transition unit target address low 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x5C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x7C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_4_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x9C)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_5_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBC)   /* IOB RX address transition unit target address high 32bit. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_BAR_DISP_SEL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE04)  /* Forward config based on BAR_NUM */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_VDM_ROUT_SEL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE08)  /* VDM message routing ways selected */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_FILTER_MODE_EP_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE10)  /* IB Filter mode control in EP mode */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NVME_REG_REMAP_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE20)  /* NVME Register Access remap control 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NVME_REG_REMAP_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE24)  /* NVME Register Access remap control 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DMA_REG_REMAP_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE30)  /* DMA Register Access remap control 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DMA_REG_REMAP_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE34)  /* DMA Register Access remap control 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AXICACHE_CTRL_REG              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1000) /* AXI CACHE Control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_RDT_SCH_WRR_WEIGHT_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1008) /* IOB_RX_RDT_SCH_WRR_WEIGHT */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_RDT_SCH_RBD_REQ_MAX_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x100C) /* IOB_RX_RDT_SCH_RBD_REQ_MAX */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ORDER_CTRL_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1020) /* Ordering control in AP IOB_RX */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ALLOC_BUF_CTRL_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1024) /* TX buffer allocation control regirster */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ORDER_TIMEOUT_REG              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1028)
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DPR_BUF_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x102C) /* Data process path buffer control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_POST_POISON_FORWARD_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1030) /* Poison posted request forward control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_POISON_FORWARD_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1034) /* Poison request forward control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_POISON_CTRL_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1038) /* Poison request control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_INT_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1040) /* Received MSI/MSIX Interrrupt contorl */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_INT_ADDR_HIGH_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1044) /* Received MSI/MSIX Interrrupt Address Window high */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_INT_ADDR_LOW_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1048) /* Received MSI/MSIX Interrrupt Address Window low */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PCIPC_MSI_INT_ADDR_HIGH_REG    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x104C) /* MSI/MSIX Interrrupt Address Window high when enable PCIPC */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PCIPC_MSI_INT_ADDR_LOW_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1050) /* MSI/MSIX Interrrupt Address Window low when enable PCIPC */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PCIPC_MSI_INT_DATA_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1054) /* MSI/MSIX Interrrupt DATA when enable PCIPC */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_LINK_MODE_NP_CRD_CTRL_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1058) /* NP credit sending max */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_LINK_MODE_P_CRD_CTRL_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x105C) /* P credit sending max */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_LINK_MODE_CPL_CRD_CTRL_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1060) /* CPL credit sending max */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_BUF_RELEASE_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1064) /* allocate buffer some times control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_HED_BUF_THRES_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1068) /* allocate hed buffer threshold */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DAT_BUF_THRES_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x106C) /* allocate dat buffer threshold */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_INT_PROT_CTRL_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E0) /* MSI/MSIX Interrupt protect control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ITF_CRD_ATU_ACTIVE_DISABLE_REG (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E4) /* Disable control for the active signal of the interface */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_RC_ATU_ADDR_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E8) /* IOB RX address transition unit base address/target addr in RC mode */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DATA_BUFFER_SIZE_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10EC) /* inbound data buffer size */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_BUFFER_THR_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F0) /* inbound buffer  threshord */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_IDLE_STS_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F4) /* inbound idle statue */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_RX_REQ_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1500) /* DFX counter for RX received request from TL */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_LOC_REQ_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1504) /* DFX counter for local request from inner module */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_SEND_AM_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1510) /* DFX counter of the request sent to AXI Master */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_SEND_LOC_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1514) /* DFX counter of the request not sent to AXI Master */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_DMA_CPL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1518) /* DFX counter of the CPL belong to DMA */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_RESP_RX_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1540) /* DFX counter of the response to TL */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_RESP_LOC_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1544) /* DFX counter of the response to inner module */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_RESP_RECV_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1550) /* DFX counter of the response from several destination */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_CNT_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F0) /* DFX conter control for IOB_RX */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_MSK_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1700) /* IOB_RX interrupt mask register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_STATUS_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1704) /* IOB_RX interrupt status register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_RO_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1708) /* IOB_RX interrupt read only status register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_SET_REG                    (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x170C) /* IOB_RX interrupt set register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_SEVERITY_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1710) /* IOB_RX interrupt severity register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_RO_CE_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1714) /* IOB_RX correctable error interrupt read only status register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_RO_NFE_REG                 (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1718) /* IOB_RX  non-fatal error interrupt read only status register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_INT_RO_FE_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x171C) /* IOB_RX  fatal error interrupt read only status register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DAT_BUF_ECC_ERR_INJECT_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1740) /* IOB_RX data buffer ECC error inject mode control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DAT_BUF_ECC_ERR_ADDR_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1744) /* IOB_RX data buffer ECC error address record */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_DAT_BUF_ECC_ERR_CNT_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1748) /* IOB_RX data buffer ECC error counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_BUF_ECC_ERR_INJECT_REG     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1750) /* IOB_RX PAB buffer ECC error inject mode control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_BUF_ECC_ERR_ADDR_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1754) /* IOB_RX PAB buffer ECC error address record */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_BUF_ECC_ERR_CNT_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1758) /* IOB_RX PAB buffer ECC error counter */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ICG_EN_REG                     (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x175C) /* IOB_RX_ICG_EN */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ICG_E_PIN_STS_REG              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1760) /* IOB_RX_ICG_E_PIN_STS */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_GLOBAL_CTRL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1800) /* Global Control of IOB_RX AML */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_MAX_TRANS_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1804) /* MAX outstanding control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_QOS_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1810) /* QOS control for AXI Master Request */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_WR_CTRL_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1820) /* Write channel control of IOB_RX AML */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_RD_CTRL_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1840)
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_ERR_RESP_CTRL_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E0) /* AXI Error response control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_ERR_WDATA_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E4) /* Error WDATA control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_IDLE_STATE_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A00) /* Idle state of the IOB_RX AML */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_MAX_TRANS_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A04) /* Max outstanding number */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_ITF_STS_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A08) /* State of the AXI Master Interface */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_TBL_PTR_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A10) /* Pointer of the ID table */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_WR_CNT_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A20) /* DFX counter 0 of the wirte operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_WR_CNT_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A24) /* DFX counter 1 of the write operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_RD_CNT_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A28) /* DFX counter of the read operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_AW_LAT_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A40) /* Write request latency DFX 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_AW_LAT_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A44) /* Write request latency DFX 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_AR_LAT_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A48) /* Read request latency DFX 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_AR_LAT_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A4C) /* Read request latency DFX 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_ERR_STS_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A60) /* Error state of the AML */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_WR_ID_STS_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A80) /* Write request ID state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_WR_ID_STS_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A84) /* Write request ID state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_RD_ID_STS_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A90) /* Read request ID state 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AML_RD_ID_STS_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A94) /* Read request ID state 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_STRMID_RD_REG              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A98) /* IOB_RX_AML_STRMID */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_STRMID_WR_REG              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A9C) /* IOB_RX_AML_STRMID */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AA0) /* IOB_RX_AML_AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AA4) /* IOB_RX_AML_AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AA8) /* IOB_RX_AML_STASH */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_SNOOP_REG                  (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AAC) /* IOB_RX_AML_SNOOP */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_GLOBAL_SEC_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB0) /* IOB_RX_AML_GLOBAL_SEC */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB4) /* IOB_RX_AML_AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB8) /* IOB_RX_AML_AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1ABC) /* IOB_RX_AML_AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AML_AXUSER_CTRL7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AC0) /* IOB_RX_AML_AXUSER */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_GLOBAL_CTRL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C00) /* Global Control Register of AXI Master Bridge */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_MAX_TRANS_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C04) /* Maximum transaction outstanding control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_QOS_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C08) /* QOS control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_ATOP_ENDIAN_FORMAT_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C10) /* Endian Format Control of inbound atomic operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_SAFETY_LEVEL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C14) /* Safety level control for AXI transaction */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_ARUSER_MODE_CTRL_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C20) /* AXIM aruser mode control for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_ARUSER_SET_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C24) /* AXIM aruser value control 0 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_ARUSER_SET_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C28) /* AXIM aruser value control 1 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_ARUSER_SET_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C2C) /* AXIM aruser value control 2 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AWUSER_MODE_CTRL_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C30) /* AXIM awuser mode control for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AWUSER_SET_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C34) /* AXIM awuser value control 0 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AWUSER_SET_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C38) /* AXIM awuser value control 1 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AWUSER_SET_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C3C) /* AXIM awuser value control 2 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_STASH_EN_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C40) /* Write Stash Enable Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_STASH_CTRL_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C44) /* Write Stash Length/Address Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_STASH_THRES_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C48) /* Write Stash frequency Control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AWUSER_SET_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C4C) /* AXIM awuser value control 3 for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AXUSER_SET_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C50) /* AXIM awuser and aruser value control for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_AXUSER_SET_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C54) /* AXIM awuser value control  for AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_ERR_RESP_CTRL_REG          (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1CE0) /* Error response control Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_AMB_ERR_WDATA_CTRL_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1CE4) /* Error write data control */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_CNT_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E00) /* DFX counter control in AMB */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_WR_CNT_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E20) /* Counter 0 of write transaction */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_WR_CNT_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E24) /* Counter 1 of write transaction */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_RD_CNT_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E28) /* Counter 0 of read transaction */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_RD_CNT_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E2C) /* Counter 1 of read transaction */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_ATOP_CNT_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E30) /* Counter for atomic operation */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_INT_NUM_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E34) /* Counter for MSI/MSI-X Interrupt */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AMB_INT_RATE_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E38) /* MSI/MSI-X Interrupt rate */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_REQ_IDLE_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E3C) /* RDT_SCH request idle */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_DPR_REQ_RDY_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E40) /* DPR req_vld and rdy */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AM_LAST_ADDR_LOW_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E44) /* AXIM last access address low */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_AM_LAST_ADDR_HIGH_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E48) /* AXIM last access address */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F00) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F04) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F08) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F0C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_4_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F10) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_5_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F14) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_6_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F18) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_7_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F1C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_8_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F20) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_9_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F24) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_10_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F28) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_11_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F2C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_12_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F30) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_13_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F34) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_14_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F38) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_15_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F3C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_16_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F40) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_17_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F44) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_18_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F48) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_19_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F4C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_20_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F50) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_21_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F54) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_22_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F58) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_23_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F5C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_24_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F60) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_25_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F64) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_26_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F68) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_27_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F6C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_28_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F70) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_29_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F74) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_30_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F78) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_RDT_QUEUE_INFO_31_REG      (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F7C) /* RD_SCH  queue info */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_GLOBAL_CTRL_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2000) /* PA Buffer global control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_SMMU_BYPASS_CTRL_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2004) /* smmu bypass enable for each port configuration register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_RETRY_CTRL_REG             (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2008) /* TLB Retry control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_TLBI_CFG_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2040) /* TLB invlaid mode configure */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2080) /* P2P global control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_OST_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2084) /* P2P outstanding control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_CREDIT_CTRL_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2088) /* P2P credit number control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_APL_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2090) /* P2P apply credit control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_APL_TIME_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2094) /* P2P credit apply time threshold register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_APL_TH0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2098) /* P2P credit apply process number threshold register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_APL_TH1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x209C) /* P2P credit apply wait number threshold register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_RLS_CTRL_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20A0) /* P2P release credit control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_RLS_TIME_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20A4) /* P2P credit release time threshold register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_RLS_TH0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20A8) /* P2P credit release processs credit threshold. */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PAB_P2P_RLS_TH1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20AC) /* P2P credit release wait credit threshold */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2APAT_LKP_REQ_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20B0) /* dfx_ib2apat_lkp_req */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2APAT_LKP_RST_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20B4) /* dfx_apat2ib_lkp_result */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_APAT2IB_LKP_RTY_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20B8) /* dfx_apat2ib_lkp_retry */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_APAT2IB_LKP_REL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20BC) /* dfx_apat2ib_lkp_release */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_APAT2IB_TLBI_REQ_REG              (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20C0) /* dfx_apat2ib_TLBi request */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2APAT_ATS_REQ_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20C4) /* dfx_ib2apat_ats request */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2APAT_ATS_ACK_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20C8) /* dfx_apat2ib_ats ack */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_CORE2IB_LKP_REQ_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20CC) /* dfx_core2ap_lookup_request */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2CORE_LKP_RST_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20D0) /* dfx_ap2core_lookup result */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2CORE_RESNED_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20D4) /* dfx_ap2core_resend */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_RBA2IB_LKP_REQ_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20D8) /* dfx_rba2ib_lookup request */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2RBA_LKP_PGFT_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20DC) /* dfx_ib2rba_lookup pagefault */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_RBA2IB_LKP_REL_REG                (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20E0) /* dfx_rba2ib lookup release */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IB2RBAT_LKP_RTY_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20E4) /* dfx_ib2rba_lookup retry */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_CMD_SYN_STS_REG                   (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20E8) /* dfx_cmd_syn_sts */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_P2P_CTRL_REG               (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2100) /* P2P DFX control register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_P2P_STATUS0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2110) /* P2P DFX status0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_DFX_IOB_RX_P2P_STATUS1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2114) /* P2P DFX status1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_CTRL_0_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2200) /* MSI/MSI-X Interrupt Address Window Contol Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_CTRL_1_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2210) /* MSI/MSI-X Interrupt Address Window Contol Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_CTRL_2_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2220) /* MSI/MSI-X Interrupt Address Window Contol Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_CTRL_3_REG            (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2230) /* MSI/MSI-X Interrupt Address Window Contol Register */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_0_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2204) /* MSI/MSI-X Interrupt Address Configuration Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_1_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2214) /* MSI/MSI-X Interrupt Address Configuration Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_2_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2224) /* MSI/MSI-X Interrupt Address Configuration Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_3_REG       (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2234) /* MSI/MSI-X Interrupt Address Configuration Register 0 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_LOW_0_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2208) /* MSI/MSI-X Interrupt Address Configuration Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_LOW_1_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2218) /* MSI/MSI-X Interrupt Address Configuration Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_LOW_2_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2228) /* MSI/MSI-X Interrupt Address Configuration Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MSI_MSIX_ADDR_LOW_3_REG        (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2238) /* MSI/MSI-X Interrupt Address Configuration Register 1 */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_0_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2300) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_1_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2310) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_2_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2320) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_3_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2330) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_4_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2340) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_5_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2350) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_6_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2360) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_EN_7_REG           (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2370) /* Enable control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2304) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2314) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2324) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_3_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2334) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_4_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2344) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_5_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2354) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_6_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2364) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ATTR_7_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2374) /* Cache attribute configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2308) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2318) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2328) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_3_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2338) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_4_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2348) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_5_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2358) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_6_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2368) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_ADDR_7_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2378) /* Address configuration for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_0_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x230C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_1_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x231C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_2_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x232C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_3_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x233C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_4_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x234C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_5_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x235C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_6_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x236C) /* Mask control for memory attribute address window */
#define HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_MEMATTR_WIN_MASK_7_REG         (HiPCIECTRL40V200_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x237C) /* Mask control for memory attribute address window */

#endif // __HIPCIEC50_AP_IOB_RX_REG_REG_OFFSET_H__
